The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2007
Filed:
Sep. 22, 2005
Niv Amit, Givat Shmuel, IL;
Ronit Bustin, Ra'anana, IL;
Lidor Goren, Netanya, IL;
Omer Heymann, Tel Aviv-Jaffa, IL;
Moshe Leibowitz, Haifa, IL;
Gil Noy, Ramat Gan, IL;
Alex Raphayevich, Kiryat Ekron, IL;
Maya Speiser, Tel Aviv-Jaffa, IL;
Niv Amit, Givat Shmuel, IL;
Ronit Bustin, Ra'anana, IL;
Lidor Goren, Netanya, IL;
Omer Heymann, Tel Aviv-Jaffa, IL;
Moshe Leibowitz, Haifa, IL;
Gil Noy, Ramat Gan, IL;
Alex Raphayevich, Kiryat Ekron, IL;
Maya Speiser, Tel Aviv-Jaffa, IL;
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects ('WMOs') for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.