The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2007
Filed:
Feb. 14, 2002
Applicants:
Ian Swarbrick, Sunnyvale, CA (US);
David Williams, Emersons Green, GB;
Inventors:
Ian Swarbrick, Sunnyvale, CA (US);
David Williams, Emersons Green, GB;
Assignee:
Clearspeed Solutions Limited, Bristol, GB;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract
A clock distribution system for an integrated circuit comprising a plurality of regions () connected by a communications bus (). Each region comprises a functional block () and at least one bus node () for connecting a respective functional block to the communications bus (). A distributed clock signal () is allowed to skew between regions, but synchronised within respective regions. A predetermined clock insertion delay () is inserted in each functional block and bus node.