The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7290159 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 30, 2007

Filed:

May. 25, 2004
Applicants:

Kirk D. Lamb, Kingston, NY (US);

Kevin C. Gower, LaGrangeville, NY (US);

Thomas J. Griffin, Salt Point, NY (US);

Steven J. Hnatko, Poughkeepsie, NY (US);

Dustin J. Vanstee, Poughkeepsie, NY (US);

Inventors:

Kirk D. Lamb, Kingston, NY (US);

Kevin C. Gower, LaGrangeville, NY (US);

Thomas J. Griffin, Salt Point, NY (US);

Steven J. Hnatko, Poughkeepsie, NY (US);

Dustin J. VanStee, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G06F 13/42 (2006.01); H04L 5/00 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A synchronous input to output protocol translator supporting multiple reference oscillator frequencies and fixed latency data computation and chip crossing circuits enables implementation of a method for delaying oscrelative to oscin a configurable way to provide a constant, minimal Tover a range of refosc frequencies between circuits for data transferred. It requires that the data transferred from a register Rbe sent over multiple wires via configurable delay circuitry for osc, capture circuitry at the input to R, and a circuit to transfer a synchronizing signal from a non-delayed clock domain to a delayed clock domain. Relative to osc, oscis a delayed, synchronous clock.


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