The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2007

Filed:

Oct. 01, 2003
Applicants:

Peter R. Pawlowski, Solana Beach, CA (US);

Mark A. Riches, San Diego, CA (US);

Inventors:

Peter R. Pawlowski, Solana Beach, CA (US);

Mark A. Riches, San Diego, CA (US);

Assignee:

Northrop Grumman Corporation, Los Angeles, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/38 (2006.01); H04L 7/02 (2006.01); H04B 17/00 (2006.01); H03D 3/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

A bit synchronizer () that includes a tapped delay line () connected to a plurality of timing hypothesis circuits. A control and adjudication circuit () is connected to the timing hypothesis circuits, and compares outputs of the timing hypothesis circuits and selects one. Each of the timing hypothesis circuits includes a sum-and-dump summer () that is connected to outputs of the tapped delay line (). The timing hypothesis circuits further include an absolute value circuit () and an averaging circuit (). A select switch () is connected to the summers () and receives a switch control signal from the control and adjudication circuit (). A threshold test circuit () compares the selected output signal to a threshold value and outputs a mark or space symbol.


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