The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2007
Filed:
Aug. 14, 2002
On Paradise, Tel Aviv, IL;
Amir Lahat, Sunnyvale, CA (US);
Zvika Bronstein, Ramat Efal, IL;
Pavel Hardak, Lod, IL;
Gila Klein, Rosh Ha'ain, IL;
On Paradise, Tel Aviv, IL;
Amir Lahat, Sunnyvale, CA (US);
Zvika Bronstein, Ramat Efal, IL;
Pavel Hardak, Lod, IL;
Gila Klein, Rosh Ha'ain, IL;
Atrica Israel Ltd., Herzelia, IL;
Abstract
A clock reconstruction mechanism for synchronous TDM communications traffic transported over asynchronous networks such as Ethernet networks. The invention is applicable to edge switches in Metropolitan Area Networks (MANs) that transport legacy TDM traffic using a Circuit Emulation Services (CES) module whereby TDM traffic is encapsulated and transported across the Ethernet network where it is de-encapsulated and clocked out to the destination. The mechanism encapsulates the input TDM data stream into Ethernet packets and inserts a network timestamp within the packet. At the destination CES, a local timestamp is generated for each received packet as it is received. The network timestamp is extracted and input along with the local timestamp to a Digital Time Locked Loop (DTLL) which is operative to accurately reconstruct the original transmit TDM clock. The filter in the DTLL performs a Least Squares Regression (LSR) algorithm and Infinite Impulse Response (IIR) filter algorithm to generate a clock control signal for adjusting the clock generated.