Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method

Abstract

Memory bank selection control circuits and methods are provided which improve the data sensing margin for data sense amplifiers in a multi-bank semiconductor memory structure. In one aspect, a bank selection signal control circuit includes a bank switch control unit that receives memory bank selection signals and outputs corresponding memory bank selection control signals to selectively connect memory banks to a global data input/output line according to a predetermined sequence. For memory bank selected prior to a last selected memory bank in the predetermined sequence, the bank switch control unit outputs memory bank selection control signals that are enabled for a first time period P, and for the last selected memory bank, the bank switch control unit outputs a memory bank selection control signal that is enabled for a second time period P, wherein Pis greater than P. A switching unit sequentially connects each selected memory bank to the global data input/output line according to the predetermined sequence, and for a predetermined period Por P, in response to the corresponding bank selection control signals.