The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2007
Filed:
May. 01, 2006
Sandra Marie Johnson, Buda, TX (US);
Shih-chung Chao, Austin, TX (US);
Nadi Rafik Itani, Austin, TX (US);
Caiyi Wang, Austin, TX (US);
Brannon Craig Harris, Austin, TX (US);
Ash Prabala, Austin, TX (US);
Douglas R. Holberg, Wimberley, TX (US);
Alan Hansford, Austin, TX (US);
Syed Khalid Azim, Fremont, CA (US);
David R. Welland, Austin, TX (US);
Sandra Marie Johnson, Buda, TX (US);
Shih-Chung Chao, Austin, TX (US);
Nadi Rafik Itani, Austin, TX (US);
Caiyi Wang, Austin, TX (US);
Brannon Craig Harris, Austin, TX (US);
Ash Prabala, Austin, TX (US);
Douglas R. Holberg, Wimberley, TX (US);
Alan Hansford, Austin, TX (US);
Syed Khalid Azim, Fremont, CA (US);
David R. Welland, Austin, TX (US);
Cirrus Logic, Inc., Austin, TX (US);
Abstract
An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.