The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2007
Filed:
Nov. 06, 2003
Seijirou Gyouten, Tenri, JP;
Sachio Tsujino, Yao, JP;
Hajime Washio, Sakurai, JP;
Eiji Matsuda, Tenri, JP;
Keiichi Ina, Tenri, JP;
Yuhichiroh Murakami, Tenri, JP;
Shunsuke Hayashi, Onomichi, JP;
Mamoru Onda, Tenri, JP;
Seijirou Gyouten, Tenri, JP;
Sachio Tsujino, Yao, JP;
Hajime Washio, Sakurai, JP;
Eiji Matsuda, Tenri, JP;
Keiichi Ina, Tenri, JP;
Yuhichiroh Murakami, Tenri, JP;
Shunsuke Hayashi, Onomichi, JP;
Mamoru Onda, Tenri, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.