The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7285867 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 23, 2007

Filed:

Nov. 03, 2003
Applicants:

Tomio Matsuzaki, Ome, JP;

Kazuyoshi Arai, Hachioji, JP;

Inventors:

Tomio Matsuzaki, Ome, JP;

Kazuyoshi Arai, Hachioji, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/28 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a semiconductor substrate having a plurality of connecting pads on one surface, an insulating film formed on one surface of the semiconductor substrate. The insulating film has holes each corresponding to one of the connecting pads, and a recess having a bottom surface depressed from the upper surface in the direction of thickness. Interconnections are formed on an upper surface of the insulating film or on the bottom surface of the recess, and connected to the connecting pads through the holes in the insulating film.


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Matsuzaki, Tomio. (2007). Wiring structure on semiconductor substrate and method of fabricating the same (U.S. Patent No. 7285867). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7285867

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