The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2007

Filed:

May. 14, 2004
Applicant:

Jae-hyuk Lee, Cheonan, KR;

Inventor:

Jae-Hyuk Lee, Cheonan, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H05K 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A chip stack package, a connecting board, and a method of connecting multiple, stacked semiconductor chips multi-chip package comprises a plurality of stacked packages including an upper package and a lower package. Each connecting board includes a board, including a wall and an opening, the wall including a top portion and a side portion, wherein the lower package may be secured in the opening; and a connecting portion, located on the top portion and the side portion of the wall. The respective packages are electrically connected by the connecting portion with one or more elements of each board/package pair being in vertical or substantially vertical alignment.


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Lee, Jae-Hyuk. (2007). Chip stack package, connecting board, and method of connecting chips (U.S. Patent No. 7285847). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7285847

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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