The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2007

Filed:

Nov. 06, 2003
Applicants:

James William Kretchmer, Ballston Spa, NY (US);

Jeffrey Bernard Fedison, Niskayuna, NY (US);

Dal Marius Brown, Schenectady, NY (US);

Peter Micah Sandvik, Guilderland, NY (US);

Inventors:

James William Kretchmer, Ballston Spa, NY (US);

Jeffrey Bernard Fedison, Niskayuna, NY (US);

Dal Marius Brown, Schenectady, NY (US);

Peter Micah Sandvik, Guilderland, NY (US);

Assignee:

General Electric Company, Niskayuna, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/76 (2006.01); H01L 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention is directed to a method for optical and electrical isolation between adjacent integrated devices. The method comprises the steps of forming at least one trench through an exposed surface of a semiconductor wafer by removing a portion of the semiconductor wafer material, forming an electrically insulating layer on the sidewalls and the bottom of the at least one trench, filling the at least one trench by conformally depositing an optically isolating material, and planarizing the semiconductor wafer surface by removing the portion of the optically isolating material above the exposed surface of the semiconductor wafer.


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