The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2007
Filed:
Apr. 24, 2003
Applicants:
Jean Belzile, Lachine, CA;
Claude Thibeault, Brossard, CA;
François Gagnon, Lachine, CA;
Naim Batani, Dollard des Ormeaux, CA;
Inventors:
Jean Belzile, Lachine, CA;
Claude Thibeault, Brossard, CA;
François Gagnon, Lachine, CA;
Naim Batani, Dollard des Ormeaux, CA;
Assignee:
Socovar S.E.C., Montreal, CA;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method and apparatus is disclosed for testing a reconfigurable logic block. Preferably, this invention is intended to be used with Field Programmable Gate Array. According to the invention, a test bus addressing unit and a test bus activation unit are used to perform a test on a logic block. Upon selection of a corresponding logic block, a test data is outputted on a test bus which enables a testing of the logic function.