The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2007

Filed:

Apr. 30, 2004
Applicants:

Richard J. Grupp, Milton, VT (US);

Gary L. Kunselman, Milton, VT (US);

Steven F. Oakland, Colchester, VT (US);

Inventors:

Richard J. Grupp, Milton, VT (US);

Gary L. Kunselman, Milton, VT (US);

Steven F. Oakland, Colchester, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is an integrated circuit chip structure that has a chip level test access port (TAP) controller and a plurality of embedded TAPs connected to the chip level TAP. Because the embedded TAPs have lengths that differ from the chip level TAP IR, and the embedded TAP IR lengths may differ from each, the chip level TAP includes a flexible length instruction register architecture adapted to accommodate the different length instruction registers of the embedded TAPs while using a constant length chip level instruction register definition for all IR accesses through the chip level TAP. Further, the invention includes selection logic adapted to actively connect only a single embedded TAP to the chip level TAP at a time.


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