The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2007

Filed:

Aug. 30, 2004
Applicants:

William Edward Atherton, Hillsborough, NC (US);

Daryl Carvis Cromer, Apex, NC (US);

Richard Alan Dayan, Raleigh, NC (US);

Scott Neil Dunham, Raleigh, NC (US);

Eric Richard Kern, Durham, NC (US);

Howard Jeffrey Locker, Cary, NC (US);

William Bradley Schwartz, Apex, NC (US);

Adam Lee Soderlund, Bahama, NC (US);

Inventors:

William Edward Atherton, Hillsborough, NC (US);

Daryl Carvis Cromer, Apex, NC (US);

Richard Alan Dayan, Raleigh, NC (US);

Scott Neil Dunham, Raleigh, NC (US);

Eric Richard Kern, Durham, NC (US);

Howard Jeffrey Locker, Cary, NC (US);

William Bradley Schwartz, Apex, NC (US);

Adam Lee Soderlund, Bahama, NC (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and system for booting up multiple PCI peripheral devices, such that the number of bootable PCI peripheral devices is not limited by the amount of computer system memory that is dedicated to storing executable boot code for the peripheral devices. The executable boot code is stored on a Read Only Memory (ROM) on each peripheral device. When a new PCI peripheral device begins to boot up, a check for available memory space in a ROM scan memory address space is performed. If there is not enough available room in the ROM scan memory address space for the new device's executable boot code, then a ROM scan detection logic pages an image of another peripheral device's executable boot code out of the ROM scan memory address space before storing the new device's executable boot code into the ROM scan memory address space.


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