The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2007
Filed:
Nov. 06, 2003
Wendy A. Belluomini, Austin, TX (US);
Ramyanshu Datta, Austin, TX (US);
Chandler T. Mcdowell, Austin, TX (US);
Robert K. Montoye, Austin, TX (US);
Hung C. Ngo, Austin, TX (US);
Wendy A. Belluomini, Austin, TX (US);
Ramyanshu Datta, Austin, TX (US);
Chandler T. McDowell, Austin, TX (US);
Robert K. Montoye, Austin, TX (US);
Hung C. Ngo, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.