The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2007
Filed:
Dec. 15, 2003
Jien-shen Tsai, Taipei, TW;
Nan-ting Yeh, Kao-Hsiung, TW;
Mou-tien LU, Hsin-Chu, TW;
Chung-chia Chen, Hsin-Chu Hsien, TW;
Shih-fang Hsiao, Hsin-Chu Hsien, TW;
Gwo-ching Lin, Tai-Chung, TW;
Sheng-chiang Chen, Miao-Li Hsien, TW;
Jien-Shen Tsai, Taipei, TW;
Nan-Ting Yeh, Kao-Hsiung, TW;
Mou-Tien Lu, Hsin-Chu, TW;
Chung-Chia Chen, Hsin-Chu Hsien, TW;
Shih-Fang Hsiao, Hsin-Chu Hsien, TW;
Gwo-Ching Lin, Tai-Chung, TW;
Sheng-Chiang Chen, Miao-Li Hsien, TW;
Springsoft, Inc., Hsinchu, TW;
Abstract
While simulating a circuit described by the netlist, a circuit simulator produces a dump file containing a set of waveform data sequences, each corresponding to a separate signal within the circuit, and representing states of its corresponding signal at a succession of times during the circuit simulation. Based on a mapping of the waveform data sequences to lines of a bus, and on transaction data models describing characteristic signal patterns appearing on the bus during each type of transaction that can occur on the bus, a transaction analysis system identifies transactions that occurred on the bus during the simulation. The transaction analysis system also notes a time during the circuit simulation in which each transaction occurred, and generates a display including a separate representation of each identified transaction positioned to represent the time the transaction occurred.