The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2007

Filed:

Oct. 06, 2005
Applicants:

Christopher Richard Doerr, Middletown, NJ (US);

Dan Mark Marom, Howell, NJ (US);

Inventors:

Christopher Richard Doerr, Middletown, NJ (US);

Dan Mark Marom, Howell, NJ (US);

Assignee:

Lucent Technologies Inc., Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B 6/26 (2006.01); G02B 6/42 (2006.01); G02B 6/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

A fully integrated microelectromechanical (MEMS) lxK wavelength selective switch (WSS) includes an array of N solid-immersion micromirrors (SIMs) and a K+1 dispersion waveguide arrays that are integrally fabricated together. In one embodiment, the WSS is fabricated in Silicon. In another embodiment, the N actuators of the SIMs are etched in the Silicon layer of a Silicon-on Insulator (SOI) wafer. Thereafter, a Silica layer is deposited on the Silicon layer and the K+1 waveguide arrays and the mirrors for the N SIMs are etched in that Silica layer. In yet another embodiment, the K+1 dispersion waveguide arrays, except for a small portion of the common confocal coupler, are fabricated using a material selected from a group including Silica, sol-gel, polymers, that is deposited on a first wafer selected from a group including Silicon, Saphire, or other glass insulator material and the remaining portion of the common confocal coupler and the N SIMs are fabricated in a Silicon wafer, and the first wafer and Silicon wafer are then butt-coupled together.


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