Write control circuitry and method for a memory array configured with multiple memory subarrays

Abstract

Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.