The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2007
Filed:
Dec. 07, 2005
Sanjay K. Charagulla, San Jose, CA (US);
Ali H. Burney, Fremont, CA (US);
Sanjay K. Charagulla, San Jose, CA (US);
Ali H. Burney, Fremont, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A method and system using a delay-locked loop (DLL) to provide multiple phase locked outputs in discrete phase intervals is disclosed. In one embodiment, a reference clock signal is transmitted through a delay chain having a plurality of delay elements. The delay chain is capable of generating a plurality of output clock signals from the reference clock signal. Each of the output clock signals are delayed in discrete phase shift intervals with respect the delay elements. A first of the output clock signals and the reference clock signal are coupled to a first phase comparator capable of forming a first DLL with the delay chain. A second of the output clock signals and the reference clock signal are coupled to a second phase comparator capable of forming a second DLL with the delay chain. The output clock signal from the first DLL or the second DLL may be programmatically selected.