The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2007

Filed:

Aug. 31, 2005
Applicants:

Duk Ho Hong, Fishkill, NY (US);

Kyoung Woo Lee, Fishkill, NY (US);

Markus Naujok, Hopewell Junction, NY (US);

Roman Knoefler, Fishkill, NY (US);

Inventors:

Duk Ho Hong, Fishkill, NY (US);

Kyoung Woo Lee, Fishkill, NY (US);

Markus Naujok, Hopewell Junction, NY (US);

Roman Knoefler, Fishkill, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g., copper (Cu)), which directly contacts the exposed portion of the first electrically conductive material. This covering step results in the definition of a wiring pattern including the first and second electrically conductive materials.


Find Patent Forward Citations

Hong, Duk. (2007). Methods of forming integrated circuit devices having metal interconnect layers therein (U.S. Patent No. 7282451). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7282451

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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