The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2007
Filed:
Aug. 15, 2005
Dae-gyu Park, Wappingers Falls, NY (US);
Cyril Cabral, Jr., Ossining, NY (US);
Oleg Gluschenkov, Poughkeepsie, NY (US);
Hyungjun Kim, Lagrangeville, NY (US);
Dae-Gyu Park, Wappingers Falls, NY (US);
Cyril Cabral, Jr., Ossining, NY (US);
Oleg Gluschenkov, Poughkeepsie, NY (US);
Hyungjun Kim, Lagrangeville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MN, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WN, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNlayer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.