The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2007

Filed:

Mar. 22, 2005
Applicants:

Osamu Goto, Miyagi, JP;

Takeharu Asano, Miyago, JP;

Motonobu Takeya, Miyagi, JP;

Katsunori Yanashima, Kanajawa, JP;

Inventors:

Osamu Goto, Miyagi, JP;

Takeharu Asano, Miyago, JP;

Motonobu Takeya, Miyagi, JP;

Katsunori Yanashima, Kanajawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a nitride semiconductor having a larger low-defective region on a surface thereof, a semiconductor device using the nitride semiconductor, a method of manufacturing a nitride semiconductor capable of easily reducing surface defects in a step of forming a layer through lateral growth, and a method of manufacturing a semiconductor device manufactured by the use of the nitride semiconductor. A seed crystal portion is formed into stripes on a substrate with a buffer layer sandwiched therebetween. Then, a crystal is grown from the seed crystal portion in two steps of growth conditions to form a nitride semiconductor layer. In a first step, a low temperature growth portion having a trapezoidal-shaped cross section in a layer thickness direction is formed at a growth temperature of 1030° C., and in a second step, lateral growth predominantly takes place at a growth temperature of 1070° C. Then, a high temperature growth potion is formed between the low temperature growth portions. Thereby, hillocks and lattice defects can be reduced in a region of the surface of the nitride semiconductor layer above the low temperature growth portion.


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