The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2007

Filed:

Apr. 25, 2005
Applicants:

Wayne Burleson, Shutesbury, MA (US);

Vishak Venkotroman, Amherst, MA (US);

Atul Maheshwari, Portland, OR (US);

Inventors:

Wayne Burleson, Shutesbury, MA (US);

Vishak Venkotroman, Amherst, MA (US);

Atul Maheshwari, Portland, OR (US);

Assignee:

University of Massachusetts, Boston, MA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Returning to FIG.sense circuitrepresents the circuit that must sense the signaling on an interconnect. NMOS deviceis always on so that there is a continuous path to ground whenever PMOS driveris on. Since leakage power is an order of magnitude less than static and dynamic power it can be omitted for clarity, although it should be noted that dynamic power increases with respect to line length since the interconnect capacitance increases as line length increases. Static power is due to flow of static current across the two resistances shown in FIG.interconnect resistanceand the resistance of transistorsandfrom FIG.represented by the resistance of equivalent NMOS transistorof FIG.


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