The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2007
Filed:
Aug. 25, 2005
Chao-cheng Lee, Hsin-Chu, TW;
Yung-hao Lin, Miao-Li Hsien, TW;
Wen-chi Wang, Yun-Lin Hsien, TW;
Jui-yuan Tsai, Tai-Nan, TW;
Chao-Cheng Lee, Hsin-Chu, TW;
Yung-Hao Lin, Miao-Li Hsien, TW;
Wen-Chi Wang, Yun-Lin Hsien, TW;
Jui-Yuan Tsai, Tai-Nan, TW;
Realtek Semiconductor Corp., HsinChu, TW;
Abstract
An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.