The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2007
Filed:
Feb. 07, 2005
John Thomas Falkowski, White Haven, PA (US);
Bruce Godley Littlefield, Oley, PA (US);
Douglas D. Lopata, Boyertown, PA (US);
Hussein K. Mecklai, Breinigsville, PA (US);
Stanley Reinhold, Allentown, PA (US);
John Thomas Falkowski, White Haven, PA (US);
Bruce Godley Littlefield, Oley, PA (US);
Douglas D. Lopata, Boyertown, PA (US);
Hussein K. Mecklai, Breinigsville, PA (US);
Stanley Reinhold, Allentown, PA (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
An integrated circuit having two or more power domains that include load circuits in different portions of the integrated circuit is disclosed. In order to conserve power, the circuits in one of the power domains are shut down by disconnecting the power source serving that domain. The load circuits in each power domain are buffered from the load circuits in other power domains by buffer cells. The buffer cells reduce leakage currents in the power domain that is shut down, by restricting data signals from the 'live' power domain from reaching the shut-down power domain, and further by providing predetermined voltage signals to the load circuits in the shut-down power domain that are selected to minimize leakage currents in the inactive load circuits. The invention further provides a corresponding method for reducing power consumption in an integrated circuit having at least two power domains separated by a buffer cell.