The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2007
Filed:
Feb. 26, 2005
Sang-jo Lee, Suwon-si, KR;
Chun-gyoo Lee, Suwon-si, KR;
Sang-hyuck Ahn, Suwon-si, KR;
Su-bong Hong, Suwon-si, KR;
Byong-gon Lee, Suwon-si, KR;
Sang-ho Jeon, Suwon-si, KR;
Yong-soo Choi, Suwon-si, KR;
Sang-Jo Lee, Suwon-si, KR;
Chun-Gyoo Lee, Suwon-si, KR;
Sang-Hyuck Ahn, Suwon-si, KR;
Su-Bong Hong, Suwon-si, KR;
Byong-Gon Lee, Suwon-si, KR;
Sang-Ho Jeon, Suwon-si, KR;
Yong-Soo Choi, Suwon-si, KR;
Samsung SDI Co., Ltd., Suwon-si, KR;
Abstract
An electron emission device includes gate electrodes formed on a substrate. The gate electrodes are located on a first plane. An insulating layer is formed on the gate electrodes. Cathode electrodes are formed on the insulating layer. Electron emission regions are electrically connected to the cathode electrodes. The electron emission regions are located on a second plane. In addition, the electron emission device includes counter electrodes placed substantially on the second plane of the electron emission regions. The gate electrodes and the counter electrodes are for receiving a same voltage, and a distance, D, between at least one of the electron emission regions and at least one of the counter electrodes satisfies the following condition: 1(μm)≦D≦28.1553+1.7060t(μm), where t indicates a thickness of the insulating layer.