The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2007
Filed:
Aug. 23, 2004
Elmehdi Aitnouri, Nepean, CA;
Edward Keyes, Ottawa, CA;
Stephen Begg, Ottawa, CA;
Val Gont, Kanata, CA;
Dale Mcintyre, Carleton Place, CA;
Mohammed Ouali, Ottawa, CA;
Vyacheslav Zavadsky, Ottawa, CA;
Elmehdi Aitnouri, Nepean, CA;
Edward Keyes, Ottawa, CA;
Stephen Begg, Ottawa, CA;
Val Gont, Kanata, CA;
Dale McIntyre, Carleton Place, CA;
Mohammed Ouali, Ottawa, CA;
Vyacheslav Zavadsky, Ottawa, CA;
Semiconductor Insights Inc., Ontario, CA;
Abstract
The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the understanding of the IC. Therefore, a number of these interconnects may be deleted from the banks in the layout data structure, provided that enough interconnects remain to maintain the electrical connectivity and the visual representation of the bank.