The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2007

Filed:

Dec. 30, 2002
Applicants:

Jeong-hoon Kook, Ichon-shi, KR;

Sang-hoon Hong, Ichon-shi, KR;

Se-jun Kim, Ichon-shi, KR;

Inventors:

Jeong-Hoon Kook, Ichon-shi, KR;

Sang-Hoon Hong, Ichon-shi, KR;

Se-Jun Kim, Ichon-shi, KR;

Assignee:

Hynix Semiconductor Inc., Kyoungki-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to implement the high-performance, the DRAM includes a plurality of normal banks, at least one cache bank, which has the same data access scheme with the normal banks, for selectively storing data with a normal bank selected at a read mode and a controller for controlling the access to the cache bank and the selected normal bank when continuous read commands are occurred to the selected normal bank.


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