Integrated semiconductor memory with an arrangement of nonvolatile memory cells, and method

Abstract

In integrated semiconductor memories whose stored information is represented by the magnitude of the ohmic resistance of layer stacks with a respective layer comprising a solid electrolyte, the problem arises that although the fact that the large threshold values (G, G) for the writing voltage and the erasure voltage differ from memory cell to memory cell means that the memory cells can be programmed individually, said memory cells cannot conventionally be erased individually, i.e., selectively in relation to the other memory cells. The reason for this is the large bandwidth of the threshold values (G) for the erasure voltages, which ranges from a potential (Verasemin) to a potential (Verasemax). The invention proposes a semiconductor memory and a method for operating the latter, in which simultaneous biasing of all the bit lines and word lines and a specific choice of the electrical potentials allow a single memory cell to be erased selectively in relation to the other memory cells.