High performance and low area write precharge technique for cams

Abstract

A technique to pre-charge a CAM block array that includes a plurality of CAM blocks that is organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to a write/search driver and one or more precharge circuits. In one example embodiment, this is accomplished by precharging each read/write bit line substantially after completing a read cycle using the one or more precharge circuits. Then, precharging each read/write bit line substantially after completing a write cycle using a write/search bit line decoder and driver circuit, followed by precharging each search bit line in the CAM block array using the write/search bit line decoder and driver circuit substantially after completing a search operation.