The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2007

Filed:

Jul. 13, 2006
Applicants:

Gregory W. Starr, San Jose, CA (US);

Wanli Chang, Saratoga, CA (US);

Kang Wei Lai, Milpitas, CA (US);

Mian Z. Smith, Los Altos, CA (US);

Richard Chang, Bloomfield, NJ (US);

Inventors:

Gregory W. Starr, San Jose, CA (US);

Wanli Chang, Saratoga, CA (US);

Kang Wei Lai, Milpitas, CA (US);

Mian Z. Smith, Los Altos, CA (US);

Richard Chang, Bloomfield, NJ (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.


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