The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2007

Filed:

Sep. 29, 2005
Applicants:

Tim Tri Hoang, San Jose, CA (US);

Sergey Yuryevich Shumarayev, San Leandro, CA (US);

IN Whan Kim, Newark, CA (US);

Thungoc Tran, San Jose, CA (US);

Inventors:

Tim Tri Hoang, San Jose, CA (US);

Sergey Yuryevich Shumarayev, San Leandro, CA (US);

In Whan Kim, Newark, CA (US);

Thungoc Tran, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A programmable logic device includes high-speed serial interface ('HSSI') circuitry that employs one or more clock signals. In addition to use of these clock signals in the HSSI circuitry, circuitry is provided for allowing at least one of these signals to be distributed throughout the PLD core circuitry, e.g., for use as an additional clock signal in the PLD core. Clock distribution is preferably done in a low-skew way.


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