The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2007

Filed:

Nov. 25, 2005
Applicants:

Guy E. Averett, Mesa, AZ (US);

Keith G. Kamekona, Scottsdale, AZ (US);

Sudhama C. Shastri, Phoenix, AZ (US);

Weizhong Cai, Scottsdale, AZ (US);

Gordon L. Bratten, Scottsdale, AZ (US);

Bladimiro Ruiz, Jr., Chandler, AZ (US);

Inventors:

Guy E. Averett, Mesa, AZ (US);

Keith G. Kamekona, Scottsdale, AZ (US);

Sudhama C. Shastri, Phoenix, AZ (US);

Weizhong Cai, Scottsdale, AZ (US);

Gordon L. Bratten, Scottsdale, AZ (US);

Bladimiro Ruiz, Jr., Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device () includes a semiconductor substrate () having a surface () formed with a first recessed region (). A first dielectric material () is deposited in the first recessed region and formed with a second recessed region (), and a second dielectric material () is grown over the first dielectric material to seal the second recessed region.


Find Patent Forward Citations

Averett, Guy. (2007). Semiconductor device and method of providing regions of low substrate capacitance (U.S. Patent No. 7276425). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7276425

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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