The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2007
Filed:
Dec. 11, 2003
Mark Charles Hakey, Fairfax, VT (US);
Steven John Holmes, Guilderland, NY (US);
David Vaclav Horak, Essex Junction, VT (US);
Charles William Koburger, Iii, Delmar, NY (US);
Peter H. Mitchell, Jericho, VT (US);
Larry Alan Nesbit, Williston, VT (US);
Mark Charles Hakey, Fairfax, VT (US);
Steven John Holmes, Guilderland, NY (US);
David Vaclav Horak, Essex Junction, VT (US);
Charles William Koburger, III, Delmar, NY (US);
Peter H. Mitchell, Jericho, VT (US);
Larry Alan Nesbit, Williston, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiOdoes not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiOis uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.