The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2007

Filed:

Oct. 08, 2004
Applicant:

Yasuhiro Ishiyama, Shiga, JP;

Inventor:

Yasuhiro Ishiyama, Shiga, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor designing apparatus capable of effectively performing a layout designing operation and capable of developing both a circuit designing operation and a layout designing operation at the same time is provided. When a layout designing operation as to a semiconductor memory circuit and a semiconductor analog circuit is manually carried out in a semi-automatic designing manner, both the circuit designing operation and the layout designing operation can be carried out at the same time, so that a designing time period can be shortened.


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