The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2007
Filed:
Jan. 07, 2005
Keiichi Kurokawa, Hyogo, JP;
Takuya Yasui, Osaka, JP;
Keiichi Kurokawa, Hyogo, JP;
Takuya Yasui, Osaka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
An automatic layout method of a semiconductor integrated circuit includes an initial arranging step for initially arranging a logic cell which constitutes the logic circuit; a placement base circuit optimizing step for applying a margin of a constant length to a wiring line length obtained from a placement so as to improve timing; an placement change restriction calculating step for calculating a placement change restriction corresponding to the margin of the constant length; and an incremental arranging step in which when a logic cell placement of a corrected logic circuit is improved, a placement improvement having the placement change restriction calculated based upon the placement change restriction calculating step is carried out.