The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2007
Filed:
Mar. 12, 2004
Mattan Kamon, Arlington, MA (US);
Gunar Lorenz, St. Remy les Chevreuse, FR;
Stephen R. Breit, Wayland, MA (US);
Mattan Kamon, Arlington, MA (US);
Gunar Lorenz, St. Remy les Chevreuse, FR;
Stephen R. Breit, Wayland, MA (US);
Coventor, Inc., Cary, NC (US);
Abstract
A system-level design and simulation environment utilizing a process specification tool that is programmatically integrated with the system level design and simulation environment thereby enabling the process-flexible design and simulation of Micro Electro-Mechanical Systems (MEMS) devices and other micro-fabricated devices is disclosed. The process specification tool is a software tool for specifying the details of the fabrication process and enables the separation of the process data from the system-level design and simulation environment. The process specification tool retrieves the process data, which may include both the process specification and material properties data. The separation of this process data from the system-level design and simulation environment allows the system-level model to have process-related parameters whose specification is not fixed, but rather is tied by reference to the process data. The tying of components to the process data allows the system-level environment to extract multiple process parameters for each component model instead of requiring duplicate entry of these parameters in each component model, a time-consuming and error prone process. Modifications of the process data are programmatically communicated to the system-level environment. The dynamic response to changes in the process data allows alternative simulations to be run more effectively and quickly than in traditional IC design environments.