The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2007
Filed:
Apr. 29, 2005
Tomas V. Colunga, Tempe, AZ (US);
Loren J. Benecke, Mesa, AZ (US);
Sribhaskar Mahadevan, Chandler, AZ (US);
Joseph S. Vaccaro, Chandler, AZ (US);
Tomas V. Colunga, Tempe, AZ (US);
Loren J. Benecke, Mesa, AZ (US);
Sribhaskar Mahadevan, Chandler, AZ (US);
Joseph S. Vaccaro, Chandler, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Built-in self test (BIST) capabilities are expanded to provide IDDQ testing of semiconductor chips. Conventional BIST modules generate vectors from a set of pseudo-random pattern generator (PRPG) values. The pseudo-random vectors generated by the set of PRPG values are simulated, and those vectors best suited for an IDDQ test are selected. Each of the IDDQ vectors are identified in a test pattern. During subsequent testing, an IDDQ test of the semiconductor chip can be performed whenever the current test vector applied by the logic BIST corresponds to one of the predetermined IDDQ states. A single test pattern based upon vectors generated by the logic BIST module can therefore be used to perform both IDDQ and stuck-at testing.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile