The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2007
Filed:
Feb. 05, 2001
David Baker, Chapel Hill, NC (US);
Christopher Basoglu, Bothell, WA (US);
Benjamin Cutler, Seattle, WA (US);
Richard Deeley, San Jose, CA (US);
Gregorio Gervasio, Sunnyvale, CA (US);
Atsuo Kawaguchi, San Jose, CA (US);
Keiji Kojima, Sagamihara, JP;
Woobin Lee, Lynnwood, WA (US);
Takeshi Miyazaki, Tokyo, JP;
Yatin Mundkur, Sunnyvale, CA (US);
Vinay Naik, Austin, TX (US);
Kiyokazu Nishioka, Odawara, JP;
Toru Nojiri, Tokyo, JP;
John O'donnell, Seattle, WA (US);
Sarang Padalkar, San Jose, CA (US);
David Baker, Chapel Hill, NC (US);
Christopher Basoglu, Bothell, WA (US);
Benjamin Cutler, Seattle, WA (US);
Richard Deeley, San Jose, CA (US);
Gregorio Gervasio, Sunnyvale, CA (US);
Atsuo Kawaguchi, San Jose, CA (US);
Keiji Kojima, Sagamihara, JP;
Woobin Lee, Lynnwood, WA (US);
Takeshi Miyazaki, Tokyo, JP;
Yatin Mundkur, Sunnyvale, CA (US);
Vinay Naik, Austin, TX (US);
Kiyokazu Nishioka, Odawara, JP;
Toru Nojiri, Tokyo, JP;
John O'Donnell, Seattle, WA (US);
Sarang Padalkar, San Jose, CA (US);
Hitachi, Tokyo, JP;
Abstract
An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I/O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I/O device driver units and external I/O devices via output pins.