The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2007
Filed:
Dec. 09, 2003
Tomoyasu Yamada, Saitama, JP;
Masaaki Shimada, Saitama, JP;
Tomoyasu Yamada, Saitama, JP;
Masaaki Shimada, Saitama, JP;
Sanken Electric Co., Ltd., , JP;
Abstract
By an NMOS () being switched on or off, a direct-current voltage Eis charged in a capacitor (), and a DC/DC converting circuit () charges a direct-current output voltage Vto be supplied to a load L in a capacitor (). A load state detection circuit () determines whether the load L is in a lightly loaded state or in a non-lightly loaded state, and outputs a signal (S) as a determination signal. When the load state detection circuit () outputs a signal (S) of 'L' as a signal representing that it is a lightly loaded state, a time period setting circuit () outputs a signal (S) of 'L' after a preset time period elapses. A PFC on/off switching circuit () is supplied with the signal (S) of “L”, and outputs a control signal (S) of “L” to a power factor improvement circuit (). Accordingly, in the case where the load L enters a lightly loaded state, the operation of the power factor improvement circuit () is stopped when the preset time elapses.