The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2007
Filed:
Jul. 26, 2005
Applicants:
Ashish Kumar Goel, Benares, IN;
Davinder Aggarwal, New Delhi, IN;
Inventors:
Ashish Kumar Goel, Benares, IN;
Davinder Aggarwal, New Delhi, IN;
Assignee:
STMicroelectronics Pvt. Ltd., Uttar Pradesh, IN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract
An improved digital circuit for reducing readback time in field programmable gate arrays (FPGAs) includes a shift register having a plurality of latches and a clock and a reset signal provided to the latches. An interconnect circuit is provided between each pair of latches of the shift register for providing a selective data frame from the desired latch or latches. Connecting a control signal generator to a control input of said interconnect circuit enables quick readback of selected data frames, thereby reducing the time consumed for debugging of an FPGA.