The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2007

Filed:

Nov. 15, 2004
Applicants:

Prashant G. Karandikar, Avondale, PA (US);

Marlene Rossing, Legal Representative, Ocean Pines, MD (US);

Inventors:

Prashant G. Karandikar, Avondale, PA (US);

Marlene Rossing, legal representative, Ocean Pines, MD (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B32B 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Ceramic-containing bodies can be bonded to other ceramic-containing bodies, or to metals or metal-containing bodies, by way of an aluminum-silicon brazing alloy. Such alloys feature high thermal conductivity and a melting range intermediate to Cu—Sil and Au—Si. By metallizing the surface of an aluminum- or silicon-containing ceramic body, for example, with silicon or aluminum, the formation of deleterious intermetallic phases at the brazing interface is avoided. This technique is particularly useful for joining reaction-bonded silicon carbide (RBSC) composite bodies, and particularly such composite bodies that contain appreciable amounts of aluminum as a metallurgical modification of the residual silicon phase. Interestingly, when the RBSC body contains minor amounts of the aluminum alloying constituent, or none, the metallization layer is not required. The resulting bonded structures have utility as mirrors, as packaging for electronics, and in semiconductor lithography equipment, e.g., as electrostatic chucks for supporting a silicon wafer during the lithography process.


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