The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2007
Filed:
Apr. 27, 2005
Method for connecting circuit elements within an integrated circuit for reducing single-event upsets
Nadim F. Haddad, Oakton, VA (US);
Neil E. Wood, Centreville, VA (US);
Adam Bumgarner, Woodbridge, VA (US);
Wayne Neiderer, Manassas, VA (US);
Shankarnarayana Ramaswamy, Chantilly, VA (US);
Scott Doyle, Centreville, VA (US);
Tri-minh Hoang, Clifton, VA (US);
Nadim F. Haddad, Oakton, VA (US);
Neil E. Wood, Centreville, VA (US);
Adam Bumgarner, Woodbridge, VA (US);
Wayne Neiderer, Manassas, VA (US);
Shankarnarayana Ramaswamy, Chantilly, VA (US);
Scott Doyle, Centreville, VA (US);
Tri-Minh Hoang, Clifton, VA (US);
BAE Systems Information And Electronic Systems Integration Inc., Nashua, NH (US);
Abstract
A method for connecting circuit elements within an integrated circuit for reducing single-event upsets is disclosed. The integrated circuit includes a first and second circuit elements that are substantially identical to each other. In order to reduce the single-event upsets to the first and second circuit elements, each of the first and second circuit elements is divided into a first sub-element and a second sub-element. The first sub-element of the first circuit element is connected to the second sub-element of the second circuit element. The second sub-element of the first circuit element is connected to the first sub-element of the second circuit element. As a result, the nodal spacings between the sub-elements within the first and second circuit elements are effectively increased without demanding additional real estate.