The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2007
Filed:
Dec. 15, 2005
Jerry C. Kao, Rochester, MN (US);
Chung-tao LI, Rochester, MN (US);
Salvatore Nicholas Storino, Rochester, MN (US);
Christophe Robert Tretz, San Jose, CA (US);
Jerry C. Kao, Rochester, MN (US);
Chung-Tao Li, Rochester, MN (US);
Salvatore Nicholas Storino, Rochester, MN (US);
Christophe Robert Tretz, San Jose, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the NAND. An output of the NAND provides an input to the inverter logic that inverts the NAND output and provides a complementary output. The NAND logic includes a series connected first sleep transistor receiving the sleep input. The first sleep transistor is turned OFF during the sleep mode. A second sleep transistor is connected between a voltage supply rail and the NAND output. The second sleep transistor is turned ON during the sleep mode to force high the NAND output and force low complementary output.