The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2007

Filed:

Jan. 24, 2005
Applicants:

Peter J. Hopper, San Jose, CA (US);

Peter Johnson, Sunnyvale, CA (US);

Kyuwoon Hwang, Palo Alto, CA (US);

Robert Drury, Palo Alto, CA (US);

Inventors:

Peter J. Hopper, San Jose, CA (US);

Peter Johnson, Sunnyvale, CA (US);

Kyuwoon Hwang, Palo Alto, CA (US);

Robert Drury, Palo Alto, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Improvements in the level of integration of a core buck and/or boost DC-DC voltage regulator sub-circuit lead to a lower manufacturing cost structure, an improved performance from lessened intrinsic parasitic resistance, a smaller die size and, thus, higher wafer yield. Further, by integrating certain components on-chip, the cost and complexity of the conventional hybrid circuit implementation is improved.


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