The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2007
Filed:
Feb. 02, 2005
Applicant:
Naoki Kiryu, Austin, TX (US);
Inventor:
Naoki Kiryu, Austin, TX (US);
Assignee:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract
Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where scan shift operations of the LBIST circuitry are performed at reduced rates. In one embodiment, a base clock signal is gated before being provided to LBIST circuitry. The clock signal is gated to produce an effective clock rate that is reduced in one or more steps from a first rate that is used in a functional phase of LBIST testing to a reduced rate that is used in a scan shift phase. The effective clock rate is stepped back up at the end of the scan shift phase to the first rate which is used in the following functional phase.