The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2007
Filed:
Aug. 30, 2005
Hideho Taoka, Komaki, JP;
Yoshihiro Suzumura, Tajimi, JP;
Kanji Hirano, Mino, JP;
Satoru Kawamoto, Owariasahi, JP;
Hideho Taoka, Komaki, JP;
Yoshihiro Suzumura, Tajimi, JP;
Kanji Hirano, Mino, JP;
Satoru Kawamoto, Owariasahi, JP;
Spansion LLC, Sunnyvale, CA (US);
Abstract
During an erasing sequence, after a preprogram operation (S), an erasing operation (S), and an APDE operation (S) are executed and confirmation by an APDE verify operation (S: P) and confirmation by an erase-verify operation (S: P) are completed, step A is executed prior to a soft-program operation (S) of a plurality of memory cells. A dummy memory cell program operation (S) is continuously executed until a completion of a program operation is confirmed by a dummy memory cell program verify operation (S). By execution of the program operation on the dummy memory cells, a voltage stress similar to that of a program operation is applied to memory cells in an over-erased state via bit lines. Thereby, the over-erased state is reduced thereby lowering a column leak current. Erroneous recognition during a soft-program verify operation (S) can be prevented, and excessive soft-programming can be avoided.