The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2007
Filed:
Jan. 16, 2004
Jun-hyung Souk, Yongin, KR;
Jeong-young Lee, Yongin, KR;
Jong-soo Yoon, Cheonan, KR;
Kwon-young Choi, Seoul, KR;
Bum-ki Baek, Suwon, KR;
Jun-Hyung Souk, Yongin, KR;
Jeong-Young Lee, Yongin, KR;
Jong-Soo Yoon, Cheonan, KR;
Kwon-Young Choi, Seoul, KR;
Bum-Ki Baek, Suwon, KR;
Samsung Electronics Co., Ltd, Suwon-si, Gyeonggi-do, KR;
Abstract
A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.