The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2007
Filed:
May. 04, 2000
Ronald A. Meck, Soquel, CA (US);
Ronald A. Meck, Soquel, CA (US);
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
The present invention, generally speaking, provides an RF power amplifier that exhibits high PAE at high output powers. The design of the power amplifier is based on the observation that the switching transistor is controlled by either voltage (for a FET) or current (for bipolar transistors), but not both. Thus, it is not necessary to develop power from the driver amplifier in order to operate the final stage as a switch. This recognition runs exactly counter to conventional wisdom, i.e., the concept of impedance matching for interstage design of high efficiency power amplifiers. It is impossible to develop solely a voltage waveform or a current waveform in a passband (resonant) network such as an RF power amplifier—both voltages and current must exist. In accordance with one aspect of the invention, however, instead of maximizing power transfer, power consumption is reduced while maintaining the magnitude of the voltage (or current) waveform. In accordance with another aspect of the invention, the driver is designed to, along with the final stage, operate in switch mode. In this instance, the design of the interstage network is similar to that of a Class E output stage. In the case of the interstage network, however, the objective is not to develop maximum power across the load (as in the case of the Class E output stage). Rather, the objective is to develop the maximum voltage across the driver's load (which is the switch input). In this arrangement, the input drive of the switch may be sufficiently high that the operating voltage of the driver stage may be reduced. This reduction further reduces the DC supply power to the driver, enhancing PAE.