The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2007
Filed:
Feb. 26, 2004
Hiroyoshi Kuge, Kanagawa, JP;
Yoshihiro Ohara, Kanagawa, JP;
Hiroyoshi Kuge, Kanagawa, JP;
Yoshihiro Ohara, Kanagawa, JP;
NEC Electronics Corporation, Kanagawa, JP;
Abstract
An area for layout of a plurality of I/O cells (called an 'I/O area') is provided in the peripheral portion of a chip and signal wirings for transferring test signals to the I/O cells are provided in the layout direction of the I/O cells. At least one empty cell provided in the I/O area at a position where I/O cells are not provided has a repeater circuit which constitutes a transfer path for the test signal. The repeater circuit receives the test signal and outputs the test signal. This structure provides a suitable semiconductor integrated circuit device adaptable for an ASIC or the like, which can adjust the delay of a test signal to be transferred along the chip's peripheral portion by suppressing an increase in the delay and degradation in waveform depression.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile